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Lab 1, January 14th 2005 :: 

I'm constructing the clock for my Skeletal Processor. This is the clock that I constructed http://www.geocities.com/neckproject/Lab1a.jpg and http://www.geocities.com/neckproject/Lab1b.jpg. This part is pretty straightforward, it only requires a number of buffers and a clock circuit. The difficult part is figuring out what type of flip-flop should we use for the RunFlipFlop. As you can see in the images that I posted, my clock unit is running just fine.


Lab 2, January 30th 2005 ::

For this part, first of all, I have to make a 12 bit register by combining a 4 bit register and a 8 bit register. This is the 12 bit register that I made http://www.geocities.com/neckproject/Lab2a.jpg. After that, I made a 12 bit T register which has 3 lines of control input which are Load, Send, and Clear http://www.geocities.com/neckproject/Lab2b.jpg. By combining 2 unit of 12 bit T register with 1 clock unit and a 16 bit bus, I constructed the MAR and PC part of the skeletal processor http://www.geocities.com/neckproject/Lab2c.jpg.  


Lab 3, February 6th 2005 ::

For this lab, I have to replace the previous PC part with a new one ( Enhanced PC ). This new PC have an Add 1 Operation which can be constructed using a 12 Bit Add 1 Unit. The 12 Bit Add 1 Unit is constructed from 12 Half Adders and 12 3 State Buffers. The Half Adder is constructed by simply attaching 2 input lines to AND and XOR Gates. The AND gate gives the value of Carry Operation, the other gate, which is XOR gate gives the value of Sum Operation http://www.geocities.com/neckproject/Lab3a.jpg. After the half adder has been constructed, I made the 12 Bit Add 1 Unit, which consists of 12 of the half adders, http://www.geocities.com/neckproject/Lab3b.jpg. After that, it's time to construct a 12 2-to-1 MUX from 3 units of 4 2-to-1 MUX with Enable line. http://www.geocities.com/neckproject/Lab3c.jpg. And then, I finished the last component of the Enhanced PC, which is a 12 bit register with 12 3-stated output lines in addition to 12 regular Q output lines. http://www.geocities.com/neckproject/Lab3d.jpg. Now all components of the Enhanced PC have been done, I simply attached all lines of the components to other corresponding lines to finish the Enhanced PC. http://www.geocities.com/neckproject/Lab3e.jpg. The final step is to replace the old PC part with this new one. http://www.geocities.com/neckproject/Lab3f.jpg.


Lab 4, February 13th 2005 ::

For this lab, I have to add some components to the previous skeletal processor. The first component is a PROM, I simply called the Notepad program from and created the hex file for the PROM. Creating a PROM is kind of easy so I didn't have any trouble working on this part. The next step is to construct a 16 bit register from 2 8 bit register. http://www.geocities.com/neckproject/Lab4a.jpg. After that, because the base processor requires a 3 state 16 bit register, so I have to construct one using the regular 16 bit register which was constructed earlier. http://www.geocities.com/neckproject/Lab4b.jpg. The final step is to put together all the components, consisting of 1 unit of 12 bit register, 1 unit of Enhanced PC, 1 unit of PROM, and 2 units of 3 state 16 bit register. http://www.geocities.com/neckproject/Lab4c.jpg.


Lab 5, February 20th 2005 ::

First stage of the CAPC processor. For this stage, I need to add a Mach part to the previous base processor. Mach part is created from 2 units of 3x8 Decoders. http://www.geocities.com/neckproject/Lab5a.jpg, After I finished the Mach part, I connected it to the RunFF which was created in Lab 1. After all wiring and stuff, I finished the CAPC processor stage 1, http://www.geocities.com/neckproject/Lab5b.jpg, how do I test to see if it's working? It's easy, first, I turned on the clock, and after that I set the clear in Enhanced PC to 1, the hex display will display a "6010", and then I set it back to 0 and the hex display will first display "1011", and then "7012", and finally "0000". It will then stop. Done!


Lab 6, February 27th 2005 ::

The second stage of the CAPC processor. For this stage, the first thing to do is creating a 4 bit zero unit. This unit is a very simple unit created from Scott's "Switches of Doom", http://www.geocities.com/neckproject/Lab6a.jpg, and then I created the 12 bit buffer from 1 unit of 4 bit buffer and 1 unit of 8 bit buffer. http://www.geocities.com/neckproject/Lab6b.jpg. Next step is to create the new PROM, with a hex file containing the data: "FFFF", "6004", "0000", "0000", and "BBBB". The details about the data can be acquired from wadanet website. After all components which are needed to finish Lab 6 are created, the next step is to wire all the components. http://www.geocities.com/neckproject/Lab6c.jpg. It's working well and it's done !


Lab 7, March 6th 2005 ::

For this lab, I only have to replace the PROM part of the CAPC processor which I created in the previous lab with a RAM. First of all, I use the wizard in the logicworks 4 to create the circuit. After that, I initialize the RAM with the value which is provided in comp212 wadanet website. http://www.geocities.com/neckproject/Lab7a.jpg. Here comes the difficult part, I have to add a 12 bit register to the processor and rewire it. After that, I'm done! http://www.geocities.com/neckproject/Lab7b.jpg.


Lab 8, March 13th 2005 ::

The third stage of the CAPC processor. For this stage, the first thing to do is wiring the output line of Q7 port of MACH (SDG) and SC3 (SubCycle 3 of the clock) to the send line of zero, the send line of buffer 12 (both are from IR), and the load line of the MAR. http://www.geocities.com/neckproject/Lab8a.jpg. The next step is to wire the output line of SDG and SC4 to the load line of MBR2, Memory (Input) Buffer Register, extend to the send line of MBR2, and finally to the NOT(/WE) line of the RAM. http://www.geocities.com/neckproject/Lab8b.jpg. The last step is to store manually the test program "FFFF" "6100" "7101" "0000" "ABCD" "0000". http://www.geocities.com/neckproject/Lab8c.jpg. With a successful run, ABCD will be displayed. Done!


Lab 9, March 20th 2005 ::

The final stage of the CAPC processor before the presentation, for this part, I constructed an ALU for the CAPC processor. http://www.geocities.com/neckproject/Lab9a.jpg >> 1 bit ALU

http://www.geocities.com/neckproject/Lab9b.jpg >> 2 bit ALU

http://www.geocities.com/neckproject/Lab9c.jpg >> 4 bit ALU

http://www.geocities.com/neckproject/Lab9d.jpg >> 8 bit ALU

http://www.geocities.com/neckproject/Lab9e.jpg >> 16 bit ALU

And then, I combine the 16 bit ALU with 2 units of 16 bit register and 1 unit of 16 bit buffer. http://www.geocities.com/neckproject/Lab9f.jpg . The next part is the wiring part. First, I put some AND gates as the AND, JMP, JMI operations for the processor. http://www.geocities.com/neckproject/Lab9g.jpg. After that, the next thing is to wire the gates to the pre constructed parts of the processor and the ALU http://www.geocities.com/neckproject/Lab9h.jpg, http://www.geocities.com/neckproject/Lab9i.jpg, http://www.geocities.com/neckproject/Lab9j.jpg . The final step of this stage is to create a test program in the PROM : "FFFF" "6100" "7200" "6101" "7201" "1200" "7202" "0000" "ABCD" "1234" "0000" "0000" "0000". Done!



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